Samsung's 3D Stacked FET wins VLSI Best Paper with triple-nanosheet channels at 42nm

Samsung’s Semiconductor Research Center has built a working 3D Stacked FET at a 42nm gate pitch, stacking n-type and p-type transistors vertically instead of placing them side by side. The design is positioned as the next step beyond Gate-All-Around (GAA): because GAA already uses layered nanosheet channels, it provides the foundation for extending transistors into the vertical dimension and packing more devices into the same chip footprint. The work scored 8.29/10 at the 2026 VLSI Symposium, ranking among the top papers out of more than 1,000 submissions and earning Best Paper recognition.

The demonstration solves three problems that make vertical stacking hard in practice. To preserve drive current despite the smaller footprint, both the upper and lower transistors use triple-stacked nanosheet channels, keeping effective channel width high. To keep current flowing cleanly, Samsung tuned its epitaxial growth process to produce uniform, defect-free silicon layers across every stacked channel — variation in thickness or crystal quality between layers would otherwise cause uneven current and device variability. Finally, a Middle Dielectric Isolation (MDI) layer separates the top and bottom transistors and serves as the structural reference for building each device’s gate stack; its position and thickness are critical, since too thin invites electrical coupling and too thick complicates gate formation.

The significance is that 3D Stacked FETs offer a path to continued logic scaling once horizontal density runs out, much like a city building upward when land is scarce. Samsung’s result shows the architecture can deliver both higher density and adequate current drive at an aggressive pitch, signaling where advanced logic nodes are likely headed after GAA.