KANs meet FPGAs: lookup-table networks hit nanosecond inference speeds

A Master’s thesis project from MIT-affiliated researchers shows that Kolmogorov-Arnold Networks (KANs) map unusually well onto FPGA hardware, enabling neural network inference at nanosecond-scale latencies that GPUs cannot touch. The work, spanning an FPGA 2026 Best Paper (KANELÉ) and an ICML 2026 paper, targets workloads where processor overhead from instruction scheduling and memory access is unacceptable — the network is compiled directly into digital logic rather than executed as instructions.

The core insight exploits a structural match between the two technologies. FPGAs are built from lookup tables (LUTs) that enumerate outputs for every binary input combination, and prior LUT-based neural networks have struggled because lookup tables are hard to train with gradient descent. KANs sidestep this: instead of scalar weights, each edge carries a learnable univariate function parametrized by B-spline coefficients. These continuous functions can be trained normally, then quantized with fixed-point arithmetic into compact LUTs — a single-variable function needs only 2^b entries, avoiding the exponential blowup that makes naive multivariate lookup tables impractical.

The second paper extends the approach from inference to online learning on the FPGA itself, leveraging the locality of B-splines (only a few basis functions are active for any input) to make on-device weight updates cheap. The significance is for domains like particle physics triggers and other real-time systems, where sub-microsecond decisions and high hardware efficiency matter more than the raw throughput GPUs provide.