Hand-built FPGA scientific calculator runs on a custom nibble-oriented soft CPU

A developer has released a complete scientific calculator implemented in hardware on an FPGA, built around a custom soft CPU designed in Verilog that operates on 4-bit nibbles rather than conventional byte- or word-sized data. The CPU runs microcode firmware that implements the calculator’s math and UI logic, and the project ships with the Verilog sources, microcode assembler, a Qt-based simulator, a command-line test harness, and Quartus synthesis files for programming real FPGA hardware.

The nibble-oriented design is a deliberate choice that matches how scientific calculators historically handled BCD arithmetic, where digits are the natural unit of computation. The toolchain is set up to run under WSL2 with Verilator for simulation and GtkWave for waveform inspection, and a WebAssembly build path is supported via an older Verilator release. Sources are released under CC BY-NC-SA 4.0.

The work is notable as an end-to-end hobbyist hardware project — covering ISA design, microcode authoring, simulation tooling, and physical FPGA deployment — and as a teaching artifact for anyone interested in how purpose-built CPUs can be tailored to a narrow application domain.